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Communications and Advanced Consumer Technologies Group
M68000
Addendum to
M68000 User Manual
August 7, 1997 This addendum to the M68000UM/AD User's Manual, Revision 8, provides corrections to the original text as well as additional information. This document and other information on this product is maintained on the World Wide Web at http://www.motorola.com/68000.
OVERVIEW
This manual includes hardware details and programming information for the MC68HC000, the MC68HC001, the MC68EC000, and the MC68SEC000. For ease of reading, the name M68000 MPUs will be used when referring to all processors. Refer to M68000PM/AD, M68000 Programmer's Reference Manual, for detailed information on the MC68000 instruction set. The four microprocessors are very similar to each other and all contain the following features: * * * * * * * Sixteen 32-Bit Data and Address Registers 16-Mbyte Direct Addressing Range Program Counter 6 Instruction Types Operations on Five Main Data Types Memory-Mapped Input/Output (I/O) 14 Addressing Modes
The following processors contain additional features: * MC68HC001/MC68EC000/MC68SEC000 -- * Statically selectable 8- or 16-bit data bus
MC68HC000/MC68EC000/MC68HC001/MC68SEC000 -- Low power
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
(c) 1997 Motorola, Inc. All Rights Reserved.
The primary features of the MC68SEC000 embedded processor include the following: * Direct Replacement for the MC68EC000 -- -- -- Pin-for-pin compatibility with the MC68EC000 in the plastic QFP and TQFP packages Vast selection of existing third-party development tools for the MC68EC000 support the MC68SEC000 Software written for the MC68EC000 will run unchanged on the MC68SEC000
* Power Management -- -- -- -- * Low-power HCMOS technology Static design allows for stopping the processor clock 3.3V or 5V operation Typical 0.5A current consumption at 3.3V in sleep mode
Software Strength -- -- Fully upward object-code compatible with other M68000 Family products M68000 architecture allows effective assembly code with a C compiler
* Upgrade -- -- Fully upward code-compatible with higher performance 680x0 and 68300 Family members ColdFire(R) code-compatible with minor modifications
1. MC68HC000
The primary benefit of the MC68HC000 is reduced power consumption. The device dissipates less power (by an order of magnitude) than the NMOS MC68000. The MC68HC000 is an implementation of the M68000 16/-32 bit microprocessor architecture. The MC68HC000 has a 16-bit data bus implementation of the MC68000 and is upward code-compatible with the MC68010 and the MC68020 32-bit implementation of the architecture.
1.1 MC68HC001
The MC68HC001 provides a functional extension to the MC68HC000 HCMOS 16-/32-bit microprocessor with the addition of statically selectable 8- or 16-bit data bus operation. The MC68HC001 is object-code compatible with the MC68HC000. You can migrate code written for the MC68HC001 without modification to any member of the M68000 Family.
1.2 MC68EC000
The MC68EC000 is an economical high-performance embedded controller designed to suit the needs of the cost-sensitive embedded-controller market. The HCMOS MC68EC000 has an internal 32-bit architecture that is supported by a statically selectable 8- or 16-bit data bus. This architecture provides a fast and efficient processing device that can satisfy the requirements of sophisticated applications based on high-level languages. The MC68EC000 is fully object-code compatible with the MC68000. You can migrate code written for the MC68EC000 without modification to any member of the M68000 Family. The MC68EC000 brings the performance level of the M68000 Family to cost levels previously associated with 8-bit microprocessors. The MC68EC000 benefits from the rich M68000 instruction set and its related high code density with low memory bandwidth requirements.
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1.3 MC68SEC000
The MC68SEC000 is a cost-effective static embedded processor engineered for low-power applications. In addition to providing the substantial cost and performance benefits of the MC68EC000, the low-power mode of the MC68SEC000 provides significant advantages in power consumption and power management. The typical current consumption of the MC68SEC000 is only 0.5A in static standby mode and 15.0mA in normal 3.3V operation. The MC68SEC000 operates in either 3.3V or 5.0V systems. The remarkably low power consumption, small footprint packages, and static implementation are combined in the MC68SEC000 for lowpower applications such as portable measuring equipment, electronic games, and battery-operated hand-held consumer products. The HCMOS MC68SEC000's static architecture is a direct replacement for the MC68EC000, which offers the lowest cost entry point to 32-bit processing. The internal 32-bit architecture provides fast and efficient processing that satisfies the requirements of sophisticated applications based on high-level languages. All of the existing third-party developer tools widely available for the MC68EC000 will directly support the MC68SEC000. You can find detailed descriptions of these tools in the High Performance Embedded Systems Source Catalog.
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2.0 SIGNAL DESCRIPTION
Change Figure 3-3 on Page 3-2.
VCC GND CLK
A23-A0
ADDRESS BUS
D15-D0 AS
DATA BUS
PROCESSOR STATUS
FC0 FC1 FC2
R/W UDS LDS DTACK MC68SEC000 BR BG BUS ARBITRATION CONTROL ASYNCHRONOUS BUS CONTROL
BERR SYSTEM CONTROL RESET HALT MODE
IPL0 IPL1 IPL2 AVEC INTERRUPT CONTROL
Figure 1. Input and Output Signals (MC68EC000 and MC68SEC000)
2.1 Data Bus (D15-D0)
In Section 3.2 on page 3-4, replace "The MC68EC000 and MC68HC001 use D7-D0 in 8-bit mode, and D15D8 are undefined." with "Using the MC68HC001, MC68EC000, and MC68SEC000 mode pin, you can statically select either 8- or 16-bit modes for data transfer. The MC68EC000, MC68SEC000, and MC68HC001 use D7-D0 in 8-bit mode. D15-D8 are undefined."
2.2 Bus Arbitration Control
In Section 3.4 on page 3-5, the sentence "In the 48-pin version of the MC68008 and MC68EC000, no pin is available for the bus grant acknowledge signal; this microprocessor uses a two-wire bus arbitration scheme." should read "In the 64-pin MC68EC000 and MC68SEC000, no pin is available for the bus grant acknowledge signal. These microprocessors use a two-wire bus arbitration scheme."
2.3 System Control
The Mode subsection heading of Section 3.6 on page 3-7 should read ``Mode (MODE) (MC68HC001/ 68EC000/68SEC000).''
2.4 MC68SEC000 Low-Power Mode
Add the following to Sections 4 and 5, Bus Operation. The MC68SEC000 has been redesigned to provide fully static- and low-power operation. This section describes the recommended method for placing the MC68SEC000 into a low-power mode to reduce the 4 M68000 USER'S MANUAL ADDENDUM MOTOROLA
power consumption to its quiescent value1 while maintaining the internal state of the processor. The low-power mode described below will be routinely tested as part of the MC68SEC000 test vectors provided by Motorola. To successfully enter the low-power mode, the MC68SEC000 must first be in the supervisor mode. A recommended method for entering the low-power mode is to use the TRAP instruction, which causes the processor to begin exception processing, thus entering the supervisor mode. External circuitry should accomplish the following steps during the trap routine: 1. Externally detect a write to the low-power address. You select this address which can be any address in the 16 Mbyte addressing range of the MC68SEC000. A write to the low-power address can be detected by polling A23-A0, R/W, and FC2-FC0. When the low-power address is detected, R/W is a logic low, and the function codes have a five (101) on their output, the processor is writing to the low-power address in supervisor mode and user-designed circuitry should assert the ADDRESS_MATCH signal shown in Figure 2 and Figure 3.
ADDRESS_MATCH AS
D CK
Q AS Q CL
D CK
Q
D CK
Q
Q CL
Q
CPU_CLK
RESTART RESET SYSTEM_CLK
Figure 2. MC68SEC000 Low-Power Circuitry for 16-Bit Data Bus
ADDRESS_MATCH AS
D CK
Q AS Q CL
D CK
Q AS Q CL
D CK
Q
D CK
Q
Q CL
Q
CPU_CLK
RESTART RESET
SYSTEM_CLK
Figure 3. MC68SEC000 Low-Power Circuitry for 8-Bit Data Bus 2. Execute the STOP instruction. The external circuitry shown in Figure 2 and Figure 3 will count the number of bus cycles starting with the write to the low-power address and will stop the processor clock on the first falling edge of the system clock after the bus cycle that reads the immediate data of the STOP instruction. Figure 3 has one more flip-flop than Figure 2 because the MC68SEC000 in
1.
The preliminary specification for the MC68SEC000's current drain while in the low-power mode is Idd < 2A for 3.3V operation and Idd < 5A for 5.0V operation.
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8-bit mode requires two bus cycles to fetch the immediate data of the STOP instruction. After the processor clock is disabled, it is often necessary to disable the clock to other sections of your circuit. This can be done, but be careful that runt clocks and spurious glitches are not presented to the MC68SEC000. A timing diagram is shown in Figure 4.
CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 CPU_CLK
AS
RW
DTACK Write to Low-Power Address Fetch Immediate Data of STOP Instruction Stop
Figure 4. MC68SEC000 Clock Stop Timing for 16-Bit Data Bus
Note: While the MC68SEC000 is in the low-power mode, all inputs must be driven to VDD or VSS, or have a pull-up or pull-down resistor.
3. This step is optional depending on whether your applications require the MC68SEC000 signals with three-state capability to be placed into a high-impedance state. To place the MC68SEC000 into a three-state condition, the proper method for arbitrating the bus (as described in 5.2 Bus Arbitration in the M68000 User's Manual, Rev 8) should be completed during the fetch of the status register data for the STOP instruction. A timing diagram with the bus arbitration sequence is shown in Figure 5.
CLK S0 S1 S2 S3 S4 S5 S6 S7 S0 S1 S2 S3 S4 S5 S6 S7 CPU_CLK
AS
RW
DTACK
BR
BG Write to Low-Power Address Fetch Immediate Data of STOP Instruction
Stop
Figure 5. MC68SEC000 Clock Stop Timing with Bus Arbitration for 16-Bit Data Bus
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After the previous steps are completed, the MC68SEC000 will remain in the low-power mode until it recognizes the appropriate interrupt . External logic will also have to poll IPLB2-IPLB0 to detect the proper interrupt. When the correct interrupt level is received, the following steps will bring the processor out of the low-power mode: 1. Restart the system clock if it was stopped. 2. Wait for the system clock to become stable. 3. Assert the RESTART signal. This will cause the processor's clock to start on the next falling edge of the system clock. Figure 6 shows the timing for bringing the processor out of the low-power mode. Both the RESTART and RESET signals are subject to the asynchronous setup time as specified in the Electrical Characteristics section of this addendum. WARNING The system clock must be stable before the RESTART signal is asserted to prevent glitches in the clock. An unstable clock can cause unpredictable results in the MC68SEC000.
CLK
CPU_CLK
RESTART
Figure 6. MC68SEC000 Clock Start Timing 4. If the MC68SEC000 was placed in a three-state condition, the BR signal must be negated before the processor can begin executing instructions.
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An example trap routine is as follows: TRAP_x MOVE.B #0,$low_power_address STOP #$2000 RTE /* Write that causes ADDRESS_MATCH to assert */ /* STOP instruction with desired interrupt mask */ /* Return from the exception */
The first instruction (MOVE.B #0,$low_power_address) writes a byte to the low-power address that will cause the external circuitry to begin the sequence that will stop the processor's clock. The second instruction (STOP #$2000) loads the SR with the immediate data. This lets you set the interrupt that will cause the processor to come out of the low-power mode. The final instruction (RTE) tells the processor to return from the exception and resume normal processing.
3.0 MC68SEC000 ELECTRICAL SPECIFICATIONS
Add to the following table to Section 10.1.
3.1 MC68SEC000 MAXIMUM RATINGS
RATING Supply Voltage Input Voltage Maximum Operating Temperature Range Commercial Extended "C" Grade Storage Temperature SYMBOL VCC Vin TA VALUE -0.3 to 6.5 -0.5 to 6.5 TL to TH 0 to 70 -40 to 85 -55 to 150 UNIT V V C
Tstg
C
3.2 CMOS CONSIDERATIONS
The following change should be made to Section 10.4, CMOS Considerations. "Although the MC68HC000 and MC68EC000 is implemented with input protection diodes, care should be exercised to ensure that the maximum input voltage specification is not exceeded." should read "Although the MC68HC000, MC68EC000, and MC68SEC000 are implemented with input protection diodes, be careful not to exceed the maximum input voltage specification."
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4.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 on page 10-6 with Figure 7.
DRIVE TO 2.4 V 2.0 V CLK 0.8 V DRIVE TO 0.5 V OUTPUTS(1) CLK A B 2.0 V 0.8 V VALID OUTPUT 0.8 V 2.0 V
2.0 V VALID n OUTPUT 0.8 V
n+1 B 2.0 V VALID OUTPUT n 0.8 V
A
2.0 V 0.8 V
OUTPUTS(2) CLK
VALID OUTPUT n+1
C DRIVE TO 2.4 V INPUTS(3) CLK DRIVE TO 0.5 V 0.8 V 2.0 V
D 2.0 V 0.8 V
VALID INPUT
C 2.0 V INPUTS(4) CLK 0.8 V
D 2.0 V 0.8 V DRIVE TO 2.4 V DRIVE TO 0.5 V
VALID INPUT
2.0 V ALL SIGNALS(5) 0.8 V E F 2.0 V 0.8 V NOTES: 1. This output timing is applicable to all parameters specified relative to the rising edge of the clock. 2. This output timing is applicable to all parameters specified relative to the falling edge of the clock. 3. This input timing is applicable to all parameters specified relative to the rising edge of the clock. 4. This input timing is applicable to all parameters specified relative to the falling edge of the clock. 5. This timing is applicable to all parameters specified relative to the assertion/negation of another signal. LEGEND: A. Maximum output delay specification. B. Minimum output hold time. C. Minimum input setup time specification. D. Minimum input hold time specification. E. Signal valid to signal valid specification (maximum or minimum). F. Signal valid to signal invalid specification (maximum or minimum).
Figure 7. Drive Levels and Test Points for AC Specifications - applies to all parts 9 M68000 USER'S MANUAL ADDENDUM MOTOROLA
5.0 MC68SEC000 DC ELECTRICAL SPECIFICATIONS
Add the following table to Section 10.13 on page 10-23. (VCC = 5.0 Vdc 5%, 3.3 Vdc 10%,; GND = 0 Vdc; TA = TL to TH)
3.3 V CHARACTERISTIC Input High Voltage Input Low Voltage Input Leakage Current BERR, BR, DTACK, CLK, I PL2-IPL0, AVEC MODE, HALT, RESET Three-State (Off State) Input Current Output High Voltage Output Low Voltage (IOL = 1.6 mA) HALT (IOL = 3.2 mA) A23-A0, BG, FC2-FC0 (IOL = 5.0 mA) RESET (IOL = 5.3 mA) AS, D15-D0, LDS, R/W, UDS Current Dissipation* f = 0 Hz f=10MHz f=16 MHz f= 20 MHz Capacitance (Vin = 0 V, TA = 25 C, Frequency = 1 MHz)** Load Capacitance HALT All Others SYMBOL VIH VIL Iin ITSI VOH VOL MIN 2.0 GND -- -- 2.4 -- -- -- -- -- -- -- -- -- -- MAX VCC 0.8 2.5 20 2.5 -- 0.5 0.5 0.5 0.5 0.7 10 15 20 20.0 70 130 MIN 2.0 GND - 0.5 -- -- VCC-0.75 -- -- -- -- -- -- -- -- -- -- 5.0 V MAX VCC 0.8 2.5 20 2.5 -- 0.5 0.5 0.5 0.5 1.0 15 25 30 20.0 70 130 UNIT V V uA uA V V
ID
mA mA mA mA pF pF
Cin CL
*During normal operation, instantaneous Vcc current requirements may be as high as 1.5A. Currents listed are with no loading. **Capacitance is periodically sampled rather than 100% tested.
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6.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS -- CLOCK TIMING (See Figure 2)
Add the following table and Figure 8 to Section 10.9 on page 10-9.
10MHz MAX 10.0 -- -- -- 10 10 16MHz min 0 60 27 27 -- -- max 16.7 -- -- -- 5 5 min 0 50 21 21 -- -- 20MHz max 20.0 -- -- -- 4 4 UNIT MHz ns ns ns
NUM. 1 2,3 4,5
CHARACTERISTIC Frequency of Operation Cycle time Clock Pulse Width Clock Rise and Fall Times
SYMBOL f tcyc tCL tCH tCr tCf
MIN 0 100 45 45 -- --
Applies to 3.3V and 5V.
1 2 2.0 V 0.8 V 4 5 3
NOTE: Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall will be linear between 0.8 V and 2.0 V.
Figure 8. MC68SEC000 Clock Input Timing Diagram
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7.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES
Add the following table and Figures 9 and 10 to Section 10.16. Applies to 3.3V and 5V. (GND = 0 V; TA = TL to TH; see Figures 3 and 4)
10MHz MIN MAX -- 35 0 35 -- 55 0 3 20 45 3 15 195 95 105 -- 15 0 0 -- 0 50 50 -- 30 30 5 0 0 -- 35 -- -- 35 -- -- -- -- 55 -- 35 35 10 -- -- -- 35 -- -- -- 110 110 16MHz MIN MAX -- 30 0 30 -- 50 0 3 15 45 3 15 120 60 60 -- 15 0 0 -- 0 30 30 -- 15 15 5 0 0 -- 30 -- -- 30 -- -- -- -- 50 -- 30 30 10 -- -- -- 30 -- -- -- 110 110 20MHz MIN MAX -- 25 0 25 -- 42 0 3 10 40 3 10 100 50 50 -- 10 0 0 -- 0 25 25 -- 10 10 5 0 0 -- 25 -- -- 25 -- -- -- -- 42 -- 25 25 10 -- -- -- 25 -- -- -- 95 95
NUM 6 6A 7 8 91 112
CHARACTERISTIC Clock Low to Address Valid Clock High to FC Valid Clock High to Address, Data Bus High Impedance (Maximum) (Write) Clock High to Address, FC Invalid (Minimum) Clock High to AS, LDS, UDS Asserted
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Address Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted (Write) 11A2 FC Valid to AS, LDS, UDS Asserted (Read)/ AS Asserted (Write) 121 Clock Low to AS, LDS, UDS Negated 13
2 2
AS, LDS, UDS Negated to Address, FC Invalid AS (and LDS, UDS Read) Width Asserted
14
14A2 LDS, UDS Width Asserted (Write) 152 AS, LDS, UDS Width Negated 16 172 181 201 20A
2,6 2 2
Clock High to Control Bus High Impedance AS, LDS, UDS Negated to R/W Invalid Clock High to R/W High (Read) Clock High to R/W Low (Write) AS Asserted to R/W Low (Write) Address Valid to R/W Low (Write) FC Valid to R/W Low (Write) R/W Low to DS Asserted (Write) Clock Low to Data-Out Valid (Write) AS, LDS, UDS Negated to Data-Out Invalid (Write) Data-Out Valid to LDS, UDS Asserted (Write) Data-In Valid to Clock Low (Setup Time on Read) AS, LDS, UDS Negated to DTACK Negated (Asynchronous Hold) Clock High to DTACK Negated
21
21A
222 23 252 262 275 282 28A
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AC ELECTRICAL SPECIFICATIONS -- READ AND WRITE CYCLES (Continued)
10MHz MIN MAX 0 -- -- 150 0 -- -- 65 0 -- -- 1.5 1.5 -- 1.5 0 5 20 0 0 20 10 1.5 1 150 35 35 3.5 3.5 55 -- 55 -- -- -- -- -- -- -- -- 16MHz MIN MAX 0 -- -- 90 0 -- -- 50 0 -- -- 1.5 1.5 -- 1.5 0 5 10 0 0 10 10 1.5 1 150 30 30 3.5 3.5 50 -- 50 -- -- -- -- -- -- -- -- 20MHz MIN MAX 0 -- -- 75 0 -- -- 42 0 -- -- 1.5 1.5 -- 1.5 0 5 10 0 0 0 10 1.5 1 150 25 25 3.5 3.5 42 -- 42 -- -- -- -- -- -- -- --
NUM 29 29A 30
CHARACTERISTIC
UNIT ns ns ns ns ns ns ns Clks Clks ns Clks ns ns ns ns ns ns Clks Clks Clks
AS, LDS, UDS Negated to Data-In Invalid (Hold Time on Read) AS, LDS, UDS Negated to Data-In High Impedance (Read) AS, LDS, UDS Negated to BERR Negated 2,5 DTACK Asserted to Data-In Valid (Setup Time on Read) 31 32 HALT and RESET Input Transition Time 33 Clock High to BG Asserted 34 Clock High to BG Negated 35 BR Asserted to BG Asserted 367 BR Negated to BG Negated 38 39 44 475 482,3 52 53 55 564 587 58A
7
BG Asserted to Control, Address, Data Bus High Impedance (AS Negated) BG Width Negated AS, LDS, UDS Negated to AVEC Negated Asynchronous Input Setup Time BERR Asserted to DTACK Asserted Data-In Hold from Clock High Data-Out Hold from Clock High (Write) R/W Asserted to Data Bus Impedance Change (Write) HALT, RESET Pulse Width BR Negated to AS, LDS, UDS, R/W Driven BR Negated to FC Driven
Applies to 3.3V and 5V.
NOTES: 1. 2. 3. 4. 5. 6. 7. For a loading capacitance of less than or equal to 50 pF, subtract 5 ns from the value given in the maximum columns. Actual value depends on clock period. If #47 is satisfied for both DTACK and BERR, #48 may be ignored. In the absence of DTACK, BERR is an asynchronous input using the asynchronous input setup time (#47). For power-up, the MC68SEC000 must be held in the reset state for 100 ms to allow stabilization of on-chip circuitry. After the system is powered up, #56 refers to the minimum pulse width required to reset the controller. If the asynchronous input setup time (#47) requirement is satisfied for DTACK, the DTACK asserted to data setup time (#31) requirement can be ignored. The data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. When AS and R/W are equally loaded (20%), subtract 5 ns from the values given in these columns. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
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S0 CLK
S1
S2
S3
S4
S5
S6
S7
6A FC2-FC0 8 6 A23-A0 7 AS 13 15 11 11A LDS / UDS 17 18 R/W 47 DTACK 27 48 31 DATA IN 47 BERR / BR (NOTE 2) 47 32 HALT / RESET 56 47 ASYNCHRONOUS INPUTS (NOTE 1) 47 32 30 29 28 9 14 12
NOTES: 1. Setup time for the asynchronous inputs IPL2-IPL0 and AVEC (#47) guarantees their recognition at the next falling edge of the clock. 2. BR need fall at this time only to insure being recognized at the end of the bus cycle. 3. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 V and 2.0 V.
Figure 9. MC68SEC000 Read Cycle Timing Diagram 14 M68000 USER'S MANUAL ADDENDUM MOTOROLA
S0 CLK
S1
S2
S3
S4
S5
S6
S7
6A FC2-FC0 8 6 A23-A0 7 AS 13 11A LDS / UDS 20A 17 18 R/W 21A DTACK 7 DATA OUT 47 BERR / BR (NOTE 2) 47 32 HALT / RESET 56 47 ASYNCHRONOUS INPUTS (NOTE 1) 47 32 30 55 26 23 48 53 25 47 28 21 20 22 15 9 11 9 14A 14 12
NOTES: 1. Timing measurements are referenced to and from a low voltage of 0.8 V and a high voltage of 2.0 V, unless otherwise noted. The voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 V and 2.0 V. 2. Because of loading variations, R/W may be valid after AS even though both are initiated by the rising edge of S2 (specification #20A).
Figure 10. MC68SEC000 Write Cycle Timing Diagram
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8.0 MC68SEC000 AC ELECTRICAL SPECIFICATIONS -- BUS ARBITRATION
Add the following table and Figure 11 to Section 10.17. (GND = 0 Vdc; TA = TL to TH; refer to Figure 13)
10MHz MIN MAX -- 55 -- 55 0 35 0 35 1.5 3.5 1.5 3.5 -- 55 1.5 5 1.5 1 -- -- -- -- 16MHz MIN MAX -- 50 -- 50 0 30 0 30 1.5 3.5 1.5 3.5 -- 50 1.5 5 1.5 1 -- -- -- -- 20MHz MIN MAX -- 42 -- 42 0 25 0 25 1.5 3.5 1.5 3.5 -- 42 1.5 5 1.5 1 -- -- -- --
NUM 7 16 33 34 35 36 38 39 47 581 58A1
CHARACTERISTICp Clock High to Address, Data Bus High Impedance (Maximum) Clock High to Control Bus High Impedance Clock High to BG Asserted Clock High to BG Negated BR Asserted to BG Asserted BR Negated to BG Negated BG Asserted to Control, Address, Data Bus High Impedance (AS Negated) BG Width Negated Asynchronous Input Setup Time BR Negated to AS, LDS, UDS, R/W Driven BR Negated to FC Driven
UNIT ns ns ns ns Clks Clks ns Clks ns Clks Clks
Applies to 3.3V and 5V.
1. The minimum value must be met to guarantee proper operation. If the maximum value is exceeded, BG may be reasserted.
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STROBES AND R/W BR
36
35 BG 33 CLK 38
34
39
NOTE: Setup time to the clock (#47) for the asynchronous inputs BERR, BR, DTACK, IPL2-IPL0, and VPA guarantees their recognition at the next falling edge of the clock.
Figure 11. Bus Arbitration Timing
CLK 47 33 BR 35 BG 39 38 AS LDS/UDS DS R/W 58A FC2-FC0 58 36 34
A23 A19-A0
D15 D7-D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V.
Figure 12. MC68SEC000 Bus Arbitration Timing Diagram
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CLK 47 33
BR 35 BG 38 AS DS VMA R/W 34
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.
Figure 13. Bus Arbitration Timing--Idle Bus Case
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CLK 47 33
BR 35 BG 16 AS DS VMA R/W 34
FC2-FC0 7 A23-A0
D15-D0
NOTE: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.
Figure 14. Bus Arbitration Timing - Active Bus Case
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CLK 47 33 BR 35 BG 38 AS DS 57A VMA R/W 58 39 39 36
FC2-FC0
A23-A0
D15-D0 NOTES: Waveform measurements for all inputs and outputs are specified at: logic high 2.0 V, logic low = 0.8 V. This diagram also applies to the 68EC000.
Figure 15. Bus Arbitration - Multiple Bus Request
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9.0 MECHANICAL DATA
9.1 PIN ASSIGNMENTS
Add Figure 12 to Section 11.1. The following defines the pin assignment and the package dimensions of the 64 lead QFP (FU package) and 64 lead TQFP (PB package) for the MC68SEC000. Note that it is pin-to-pin compatible with the MC68EC000.
GND
UDS
LDS
D10
64 R/W DTACK BG BR VCC CLK GND MODE HALT RESET AVEC BERR IPL2 IPL1 IPL0 FC2 16 17 1
49 48
D11
AS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D12 D13 D14 D15 A23 A22 A21
MC68SEC000FU/PB
VCC A20 A19 A18 A17 A16 A15 A14 33 32 A13
FC1
FC0
A0
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
A10
A11
Figure 16. 64-Lead Quad Flat Pack and 64-Lead Thin Quad Flat Pack
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A12
21
10.0 PACKAGE DIMENSIONS - FU SUFFIX
This diagram replaces the one on Page 11-16 64 Lead Quad Flat Pack Case 840B-01
R G H M
A
B
S
D K C
L
DIM A B C D G H K L M R S
MILLIMETERS MIN 16.95 13.90 16.95 13.90 0.30 0.80 BSC 2.15 0.13 2.00 12.00 REF 12.00 REF 2.45 0.23 2.40 0.085 0.005 0.79 MAX 17.45 14.10 17.45 14.10 0.45 MIN 0.667 0.547 0.667 0.547 0.012
INCHES MAX 0.687 0.555 0.687 0.555 0.018 0.031 BSC 0.096 0.009 0.094 0.472 REF 0.472 REF
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M68000 USER'S MANUAL ADDENDUM
MOTOROLA
11.0 PACKAGE DIMENSIONS - PB SUFFIX
Add the following to Section 11.2. 64 Lead Thin Quad Flat Pack Case 840F-02
G H M
A1 B1
A
B
D1 C1 D C
L K
DIM A A1 B B1 C C1 D D1 G H K L M
MILLIMETERS MAX 12.00 BSC 6.00 BSC 10.00 BSC 5.00 BSC 12.00 BSC 6.00 BSC 10.00 BSC 5.00 BSC 0.17 0.27 0.50 BSC --1.60 0.09 0.20 1.35 1.45 MIN
INCHES MIN 0.472 BSC 0.236 BSC 0.394 BSC 0.197 BSC 0.472 BSC 0.236 BSC 0.394 BSC 0.197 BSC 0.007 0.020 BSC --0.004 0.053 0.063 0.008 0.057 0.011 MAX
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
23
12.0 PACKAGE/FREQUENCY AVAILABILITY
Replaces Section 11.1 The following tables identify the packages and operating frequencies available for the MC68HC000, MC68HC001, MC68EC000, and the MC68SEC000.
MC68SEC000 PACKAGE Quad Flat Pack (FU) FREQUENCY 10 MHz 16 MHz 20MHz 10 MHz 16 MHz 20MHz VOLTAGE 3.3 V 5V
Thin Quad Flat Pack (PB)
MC68HC000 PACKAGE Plastic DIP Plastic Quad Pack (PLCC) Plastic Quad (Gull Wing)** Pin Grid Array, Solder Lead Finish** Pin Grid Array, Gold Lead Finish** Plastic Quad Pack (PLCC) MC68HC001** PACKAGE Plastic Quad Pack (PLCC) Plastic Quad (Gull Wing) Pin Grid Array, Gold Lead Finish
FREQUENCY 8,10,12,16,20 MHz 8,10,12,16,20 MHz 8,10,12,16,20 MHz 8,10,12,16,20 MHz 8,10,12,16,20 MHz
VOLTAGE 5V 3 3 3 3 3 VOLTAGE 5V
FREQUENCY 8,10,12,16 MHz 8,10,12,16 MHz 8,10,12,16 MHz 8,10,12,16 MHz
MC68EC000 PACKAGE Plastic Quad Pack (PLCC) Plastic Quad Flat Pack
FREQUENCY 8 MHz 10 MHz 12 MHz 16 MHz 20 MHz
VOLTAGE 5V
NOTE : ** not recommended for new designs
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M68000 USER'S MANUAL ADDENDUM
MOTOROLA
ORDERING INFORMATION
Add the following to Section 11. The following tables contains the ordering information for the MC68SEC000. MC68SEC000 Ordering Information
PACKAGE QFP TQFP BODY SIZE 14.0 mm X 14.0mm 10.0mm x 10.0mm LEAD SPACING 0.8mm 10/16/20 MHz 0.5mm 3.3V or 5.0V SPEED (IN MH Z) VOLTAGE SUFFIX FU CFU PB CPB TEMPERATURE RANGE 0C to +70C -40C to +85C 0C to +70C -40C to +85C
MC68HC000 Ordering Information
PACKAGE DIP PLCC BODY SIZE 81.91mm X 20.57mm 25.57mm X 25.27mm LEAD SPACING 2.54mm 1.27mm SPEED (IN MHZ) 8, 10, 12, 16 8, 10, 12, 16, 20 8, 10, 12, 16 VOLTAGE 5.0V SUFFIX P FN CFN TEMPERATURE RANGE 0C to +70C 0C to +70C -40C to +85C
MC68EC000 Ordering Information
PACKAGE PLCC PQFP BODY SIZE 25.57mm X 25.27mm 14.1mm X 14.1mm LEAD SPACING 1.27mm 0.8mm SPEED (IN MHZ) 8, 10,12, 16, 20 8, 10,12, 16, 20 VOLTAGE 5.0V SUFFIX FN FU TEMPERATURE RANGE 0C to +70C
DOCUMENTATION
Add to Section 11. The documents listed in the following table contain detailed information that pertain to the MC68SEC000 processor. You can obtain these documents from the Literature Distribution Centers listed on the last page of this document. MC68SEC000 Documentation
MC68SEC000 DOCUMENTATION M68000 Family Programmer's Reference Manual M68000 User's Manual High Performance Embedded Systems Source Catalog`` MC68EC000 Product Brief MC68SEC000 Product Brief DOCUMENT NUMBER M68000PM/AD M68000UM/AD BR729/D MC68EC000/D MC68SEC000/D
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
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